`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    03:27:06 10/14/2013 
// Design Name: 
// Module Name:    TopNexys2 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module TopNexys2(
    input        clk,
    inout  [7:0] DB, // these are all wires for Depp protocol
    input        EppWRITE,
    input        EppASTB,
    input        EppDSTB,
    output       EppWAIT,
    output [6:0] seg, // 7 seg 
    output       dp,
    output [3:0] an,
    output [7:0] Led,
    input  [7:0] sw,
    input  [3:0] btn,
    inout        PS2C,
    inout        PS2D,
    output [3:1] vgaRed,
    output [3:1] vgaGreen,
    output [3:2] vgaBlue,
    output       Hsync,
    output       Vsync,
    inout  [7:0] JA,
    inout  [7:0] JB,
    inout  [7:0] JC,
    inout  [3:0] JD	
    );
 
    // On Nexys2 Led[0:3] is connected to JD[7:4], ie. JD[7]=Led[0], JD[6]=Led[1], etc.
    BoardConfiguration boardConfigurationInstance(clk, clk,
        EppASTB, EppDSTB, EppWRITE, EppWAIT, DB,
        Led, sw, btn, seg[6:0], dp, an,
        PS2C, PS2D, /*PS2C_fake*/, /*PS2D_fake*/, //these ports are available on other boards.
        vgaRed, vgaGreen, vgaBlue, Hsync, Vsync,
        JA, JB, JC, JD[3:0]);

endmodule
